The present invention relates to selecting chips within a stacked semiconductor package using through-electrodes.
In the semiconductor industry, packaging technologies for integrated circuits have continuously been developed to satisfy the demand toward miniaturization and mounting reliability. Recently, as miniaturization and high performance in demand for electric and electronic products, various stacking techniques have been developed.
The term “stack” that is referred to in the semiconductor industry means to vertically place together at least two semiconductor chips or semiconductor packages. In the case of a memory device, by using stacking technology, it is possible to realize a product having memory capacity at least two times greater than without stacking. Since stacked semiconductor packages have advantages in terms of not only memory capacity but also mounting density and mounting area utilization efficiency, research and development for stacked semiconductor packages have accelerated.
Use of through-electrodes have been proposed for stacked semiconductor packaging. For this type of package, through-electrodes are formed in semiconductor chips such that the semiconductor chips can be electrically connected by the through-electrodes.